The development environment hosts and manages design projects. It features flow control algorithms to display and control the flow of development. The suite works with electronics and contains multiple layouts for schematics and multi-device projects.
CADSTAR is a powerful PCB design solution that allows an intuitive work flow, guiding designers easily through their design process. CADSTAR incorporates all the technologies necessary for a complete electronic development process in a single environment. The full range of the solution includes schematics, board- and FPGA-level system design, PCB layout, high-speed and signal integrity, analysis, 3D, and more.
v13.0 [Nov 24, 2011]
CADSTAR now supports a new Constraint Browser tool which allows constraints to be set during schematic development. Alongside this is an enhanced constraint management system that makes the Constraint Browser and Constraint Manager the master when handling constraints, allowing for more advanced constraint management.
CADSTAR now contains tools allowing design data to be exported to IDF. IDF data can also be imported into CADSTAR to update designs.
DXF Import now allows BLOCK, ELLIPSE, SPLINE and POLYLINE data to be imported. Objects of the same type defined on different layers can now imported onto one layer in CADSTAR. The DXF design can now be automatically shifted to fit within the CADSTAR design area.
Drill letters and the drill table, previously only available in the drill drawing output, can now be added to and edited on the PCB drawing canvas. Furthermore drill letters can now be generated automatically.
Selection Method is a new setting that has been added. It gives more control over how items are selected during Frame Select, Polygon Select and Freehand Select. When Selection Method is set to Cover, only items completely covered by the selection shape are selected.
Running applications from the Tools menu (such as PREditor XR) no longer minimises CADSTAR allowing cross probing to be performed. It is now possible to cross probe groups of items.
The default behaviour of CADSTAR has changed. When editing symbols, certain changes are applied to all symbols (gates) with the same name. Similarly connector pins can be edited and certain changes are applied to all pins on the same connector.
The Bus Report, Electrical Rules Report, Routing Completion Report, Unused Component Report and Design Rules Check Report can now be viewed as Dockable Windows.
The grids used in Library Editor have been updated giving several GUI benefits. Select Symbol/Component Name dialog now displays a preview of the currently selected item. Part Definition Symbol/Component view updated to allow mouse wheel panning and zooming.
A fully interactive Mirror View of the PCB has been introduced.
Mirror and 1:1 Scaling options have been included in the Print options for all design types, including in the Library Editor.
Undo / Redo Support has been implemented for Part Reload, Part Replace and Manual Gate / Pin Swap functionality. The Keep Swap dialog has been removed meaning fewer clicks are required when performing a manual swap.
For interactive operations in Schematic Designs a check is now performed to prevent overlapping connections on different nets. A new report has also been added which checks for overlapping connections.
It is now possible to retain local reference names and pad information when reloading parts.
The Assignments dialog now allows assignments (including any reassignments) to be duplicated with a single button click.
It is now possible to keep the original alternate name when replacing or reloading parts.
Two new settings have been added that allow Pad / Via - Profile errors to be ignored while pouring copper.
When an additional gate/connector pin of an existing part is added, the variant information and fitted status will be copied from the existing gates/connector pins to the newly added gate/connector pin. Adding additional gates/connector pins that are not part allocated will copy variant information and fitted status from existing gates/connector pins with the same symbol name.
When performing ECO updates, Back Annotation and RINF imports you can now automatically add all unmatched assignments of a given type.
In a schematic design connector pins are now automatically part allocated.
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