Deeds: Digital Electronics Education and Design Suite is a set of educational tools for Digital Electronics. It covers various areas of digital electronics, like combinational logic networks, sequential logic networks, custom circuit blocks design, micro-computer programming, and more. The program helps students learn to design (and test) electronic systems, test digital systems on FPGA boards, and more.
v1.8 [Mar 29, 2014]
- Internal file version has changed (to 1.024), so files saved with the current 1.80 Deeds version cannot be opened in previous versions. However, as usual, backward compatibility is maintained: current version can read all the previous versions’ files.
- Counter components have been modified: in the new counter family, the “Terminal Count” output (Tc) can be disabled. For compatibility reasons, the previous counter type parts (used until version 1.71) are still available, but have been moved to the obsolete components library (see the menu command: “Circuit/Components/Old Library”).
- The counters have two enable inputs: En (Enable count) e Et (Enable Terminal Count). When Et and En are both “high”, counting is enabled. When Et is “high”, Tc is always generated, even when counting is disabled. When En is “high”, counting and Tc are enabled only when Et is “high”, while Et is “low”, it disables both counting and the generation of Tc.
- Register components, except the "universal shift registers", have been modified. The old components have been moved to the obsolete components library.
- The PIPO, PISO and SIPO components are characterized by the addition of an “Enable” input ('E'). A few pins have changed position. An important change on the PISO registers: the load input LD is now ‘synchronous’ and ‘active high’.
- In the “Test on FPGA” expert window, the "Slow Clock Mode" and "Step by Step Mode" have been extended. Now it is possible to reach, when automatic execution is set, respectively, up to 100 clock cycles and 100 instructions per second.
- Fixed a bug, in the “Test on FPGA” expert window: erasing an association previously done, when the circuit file was closed, a non-recoverable error occurred.
- When a “simulation by animation” was running, printing the circuit produced either an empty or incomplete print. The problem has been fixed, by temporary disabling the animation during the print process.
- Now, if the d-DcS tries to read a file generated by a newer d-DcS version, the warning message says: 'Newer d-DcS file format! Download and install the last Deeds Version'.
- Regarding the VHDL export of a d-FsM file, a bug has been fixed. In order to avoid the generation of input/output names non-compliant with the VHDL rules, the d-FsM adds the initial string "o_" to all outputs, and the string "i_" to all inputs. In this way, the name will never be equal to a reserved VHDL identifier.
A date with: a Ghost girl
